Substrate Package Designer with Security Clearance

Piper Companies is looking for a Substrate Package Design to join a cutting-edge semiconductor team onsite Monday through Friday in Saratoga, CA . The ideal Substrate Package Designer will lead the physical layout of advanced multi-die substrates that integrate multiple chiplets into a high-density, high-performance package. Responsibilities for the Substrate Package Designer: * Lead the physical layout of complex multi-die substrates while supporting chiplet-based integration. * Collaborate with package integration, signal/power integrity, and mechanical teams to ensure successful layout implementation. * Drive routing feasibility and co-design alignment with floor planning, mechanical, and system constraints. * Own the full layout process, ensuring performance, manufacturability, and design quality. * Use industry-standard tools like Cadence Allegro APD and AutoCAD to execute and refine substrate designs. Qualifications for the Substrate Package Designer: * 8 years of experience in substrate layout design for advanced packaging. * Must be eligible to work in the United States and obtain and maintain an Active U.S. Government Secret Clearance. * Strong background in physical layout and collaboration with ASIC, signal, and power teams. * Experience with packaging technologies such as CoWoS, FPGA, CPU, GPU, and/or MCM. * Proficient in Cadence Allegro APD and AutoCAD design tools. * Bachelor's degree in Electrical Engineering preferred. Compensation/Benefits for the Substrate Package Designer: * Salary Range: $160,000 - $190,000 annually * Comprehensive Benefits: Medical, Dental, Vision, 401K, PTO, Sick Leave (if required by law), and Holidays This job opens for applications on 11/4/2025. Applications for this job will be accepted for at least 30 days from the posting date. Keywords: Package Layout, Substrate Design, Multi-Die Integration, Chiplet Packaging, Escape Routing, Signal Integrity, Power Delivery, Cadence Allegro APD, AutoCAD, CoWoS, MCM, GPU, CPU, FPGA, Semiconductor Layout, ASIC, packaging technology, Package Design, Package Design Engineer LI-BR1 LI-ON SITE

Location: Saratoga, New York, US

Posted Date: 11/12/2025