Principal Analog Design Engineer

Overview Principal Analog Design Engineer Pavia, Italy €85,000 to €110,000 Bonus SIGNING BONUS Paid Relocation This role is a key position within our Optical PHY (CE-OPHY) team, which is part of our Central Engineering division. Our team is at the forefront of designing high-speed and optical transceivers for modern communication infrastructure. This technology is critical for addressing the explosive demand for bandwidth in mega data centers that power social media, video-on-demand, gaming, and other real-time data streams. We are dedicated to developing innovative, first-to-market chips and subsystem solutions that push the boundaries of data rates and power efficiency. Key Responsibilities Design & Architecture: Analyze and interpret block specifications, owning transistor-level design and selecting the most appropriate topologies. Design entire analog macros or IPs from concept to mass production. Verification & Validation: Model and validate circuit blocks, supervise layout activities, provide guidelines, and conduct post-layout verifications to ensure design integrity. Collaboration & Leadership: Collaborate with other engineering teams to enhance existing solutions, participate in cross-functional meetings, and train/mentor junior designers to build the team\'s expertise. Project Management: Manage pre-silicon tasks (simulation and modeling) and post-silicon tasks (lab characterization, debugging, correlating measurements to simulations) through to high-volume production. Candidate Profile Education & Experience: Master\'s degree or PhD in Electrical Engineering or related field; 12-15 years of professional experience. Technical Skills: Proven experience in IC design from architecture definition to lab characterization and volume production. Strong background in analog design (multi-GHz range), supervision of custom analog layout, use of standard EDA tools, and debugging to correlate simulations with measurements. Preferred Qualifications: Experience with multi-Gbps electrical SerDes or electro-optical transceivers; knowledge of advanced CMOS nodes including FinFET is advantageous. Personal Skills: Strong communication, presentation, and documentation abilities. Proficiency in Italian and English (minimum B2) for an international team. Work Model: On-site, full-time position located in Pavia, Italy. J-18808-Ljbffr

Location: Cascina Vignazza, Lombardia, IT

Posted Date: 11/9/2025