Senior Back-End Engineer – Drive Next‑Gen Chip Tape‑Outs (Floorplanning & P&R)

️ Senior Back-End Engineer – Drive Next‑Gen Chip Tape‑Outs (Floorplanning & P&R) Location: Barcelona, Spain (On-site) ️ Language Requirement: English (C1 minimum) Contract: Permanent – Internal team of our partner ️ Visa Sponsorship: Available Industry: Semiconductors, RISC-V, High-Performance Computing Build the Physical Foundations of the RISC-V Revolution Akuaro is excited to be leading the recruitment for our partner — a European deep-tech company at the forefront of high-performance computing and semiconductor innovation. Specialized in RISC-V high-performance processors and backed by major European initiatives, our partner is assembling a world-class team in Barcelona. They are now seeking a Senior Back-End (Physical Design) Engineer with extensive expertise in synthesis, place-and-route, and timing closure to turn next-generation chip designs into reality at advanced process nodes. ⚡ Why This Role Is Unique Play a key role in one of the first RISC-V high-performance chip tape-outs in Europe. Tackle the challenges of designing in bleeding-edge process nodes (advanced nanometer technologies). Own the entire physical design flow – from netlist synthesis to GDSII sign-off – and see your work manufactured in silicon. Integrate custom IP and innovate in clock tree design and power optimization for a brand-new processor architecture. Be part of Europe’s semiconductor renaissance, building a cutting-edge product in a dynamic startup environment. Your Mission As a Senior Back-End Engineer, your mission is to ensure that our partner’s cutting-edge RISC-V processor designs are efficiently and successfully implemented in silicon. You will architect and execute the full physical design flow – from RTL synthesis and floorplanning through place-and-route to final timing closure and sign-off – for a complex System-on-Chip. Working closely with front-end designers, you’ll influence design choices for physical optimizations, solve challenging puzzles in timing/power, and ultimately achieve a successful tape-out on schedule for an advanced technology node. What You’ll Be Doing Run RTL synthesis for large-scale designs, optimizing for timing, area, and power. Plan and execute floorplanning and power planning for a complex SoC in an advanced process node. Develop and refine place-and-route (P&R) flows using industry tools (Synopsys ICC2, Cadence Innovus, or equivalent) to meet design constraints. Perform Clock Tree Synthesis (CTS) and design robust clock distribution networks (including custom clock tree solutions as needed). Integrate various blocks and custom IP (memories, analog macros) into the chip layout, managing block pin placements and routing resources. Conduct Static Timing Analysis (STA) across multiple modes and corners; iterate to achieve timing closure at target frequencies. Run power analysis (using tools like PrimeTime PX or RedHawk) to guide power optimization and ensure the design meets power budgets. Perform and oversee physical verification checks – resolve DRC/LVS violations and ensure the design meets all foundry sign-off criteria. Collaborate with DFT engineers on scan chain insertion, BIST, and ensure DFT requirements are met (Tessent or similar flows as a plus). Continuously refine scripts (Tcl, Python) to automate flows, improve P&R throughput, and generate reports for key metrics. Mentor junior engineers or provide technical leadership in physical design discussions, leveraging your experience across multiple tape-outs. ✅ What You Bring Bachelor’s, Master’s, or PhD degree in Computer Science, Electrical/Electronic Engineering, or related field. 7 years of industry experience in back-end physical design of complex ASICs or SoCs. Hands-on expertise with EDA tools from Synopsys, Cadence, or Mentor for synthesis, place-and-route, and sign-off. Proficiency in Tcl scripting (and optionally Python) for automating EDA tool flows and optimizing design processes. Track record of at least 2 successful chip tape-outs (from netlist to GDSII) in advanced technology nodes. Deep knowledge of timing closure techniques and sign-off timing analysis (cross-corner, OCV, multi-mode). Experience with clock tree synthesis (CTS) and familiarity with complex clocking (gated clocks, multiple clock domains). Strong understanding of power analysis/optimization and using tools like PrimeTime PX to reduce power consumption. Knowledge of physical verification and sign-off checks: DRC, LVS and how to fix associated issues. Familiarity with DFT concepts and exposure to flows (e.g., Mentor Tessent) is a plus. Excellent problem-solving skills and meticulous attention to detail in identifying and fixing physical design issues. Team player with effective communication skills, able to work closely with front-end, DFT, and verification teams. English fluency (C1 or higher) . What’s in It for You Flexible working hours – Outcome-driven culture with understanding of work-life balance. Competitive pay – Salary commensurate with your experience and the critical role you’ll play. Continuous learning – Work on cutting-edge tech in advanced nodes; broaden your skillset with new challenges. ✈️ Relocation support – Visa sponsorship available for international candidates ready to join us in Barcelona. ☕ Snacks, coffee, and free Spanish lessons – Friendly office environment to make you feel at home in a new city. Barcelona lifestyle – Enjoy sun, sea, and a thriving tech scene at our headquarters. Ready to Build the Future of Chips in Europe? If you’re passionate about physical design and want to shape one of Europe’s most exciting semiconductor projects, we want to hear from you. Apply now — Akuaro is exclusively managing this hiring process for our partner. Let’s talk and explore this opportunity further.

Location: Catalonia, ES

Posted Date: 8/4/2025