Senior Design Verification Engineer

Senior ASIC Verification Engineer | AI Semiconductor Start-up | Amsterdam, NL A fast-growing Semiconductor scale-up are looking for an experienced ASIC Verification Engineer to join their team, and help define the next generation of security-focused CPU Chips. As a UVM Verification Engineer, you will play a key role in ensuring the quality and reliability of our cutting-edge products. Leveraging your extensive experience with Universal Verification Methodology (UVM) and verification techniques, you will contribute to the development of robust verification environments and methodologies. You will collaborate closely with cross-functional teams including design, architecture, and software engineering to deliver high-quality solutions that meet or exceed customer expectations. Responsibilities Develop and maintain UVM-based verification environments for complex digital designs. Create comprehensive verification plans and test cases based on design specifications. Implement and execute test benches to verify functionality, performance, and compliance with specifications. Debug issues and work closely with design engineers to resolve them in a timely manner. Drive continuous improvement of verification methodologies, processes, and best practices. Mentor junior team members and provide technical guidance as needed. Collaborate with other teams to ensure alignment of verification efforts with project timelines and goals. Participate in design reviews and contribute to architectural decisions from a verification perspective. Requirements Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 5 years of experience in ASIC verification. Development and deployment of large SoCs on emulation platforms Practical experience of verifying on processor-based system designs Experience verifying subsystems for PCIe, DDR, UCIe, Ethernet Knowledge of C/C++ and/or hardware verification languages e.g. (SystemVerilog, SystemC), shell programming/scripting (g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies – UVM/OVM, formal, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation and support HW/SW Co-simulation/emulation, QEMU Interested? Apply directly through LinkedIn, or send your CV to george@eu-recruit.com By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/).

Location: Nederland, NL

Posted Date: 6/23/2025