RTL Design Verification Engineer

RTL Design Verification Engineer Role Overview: Responsible for verifying RTL designs using SystemVerilog and UVM to ensure design correctness and functionality before chip fabrication. Key Responsibilities: Develop test plans and UVM-based test suites Conduct IP , module , subsystem , and SoC-level verification Perform testbench linting and formal assertion checks Verify low-power features and create emulation and FPGA prototypes Skills Required: Strong proficiency in SystemVerilog and UVM Experience in formal verification and low-power design validation Familiarity with emulation models and FPGA prototyping Ability to develop scalable and reusable verification environments

Location: México, MX

Posted Date: 6/14/2025