DFT Engineer - SoC/ASIC

Job Description : Key Responsibilities : 1. Develop and implement DFT architecture for complex SoC/ASIC designs. 2. Integrate DFT features such as scan chains, BIST (Memory BIST, Logic BIST), JTAG (IEEE 1149.1), and boundary scan. 3. Work closely with RTL, Verification, and Physical Design teams to ensure seamless DFT integration. 4. Perform ATPG (Automatic Test Pattern Generation) and fault grading using tools like Tessent, Synopsys DFT tools, etc. 5. Analyze test coverage and work to optimize test strategies to improve fault coverage and reduce test time. 6. Support silicon bring-up and post-silicon validation. 7. Debug and resolve test-related issues during simulation, emulation, and silicon test phases. 8. Collaborate with manufacturing teams to develop test programs for ATE platforms. Requirements : 1. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 2. 6 years of relevant experience in DFT implementation and validation. 3. Solid understanding of digital design fundamentals and DFT concepts. 4. Hands-on experience with industry-standard DFT tools. 5. Proficiency in scripting languages (Python, Perl, Tcl) for automation. 6. Knowledge of RTL (Verilog/System Verilog), simulation, and verification flows. 7. Familiarity with STA, synthesis, and physical design flows as they relate to DFT. (ref:hirist.tech)

Location: hyderabad, IN

Posted Date: 5/15/2025