Semiconductor Design Engineer

1. Hands-on experience in developing/understanding building block schematics, memory schematics 2. running circuit simulation with spice simulators, DC analysis, transient analysis. 3. Experience in deciphering circuit behaviour from schematics. 4. Familiarity with circuit characterization, timing libraries - files and formats, timing arcs 5. Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations. 6. Familiarity with static timing analysis 7. Hands-on experience in Gate level simulations with SDF back annotation. 8. Debug SDF annotation issues and ensure good annotation coverage. 9. Hands-on experience with latch based designs and their timing requirements. 10. Debugging Gate level simulation failures and root causing the failures to actual circuits. 11. what-if analysis by doing the change and making sure the fix can solve the issue. 12. Hands-on knowhow of System Verilog Assertions to specify expected design behaviour 13. Familiarity with UVM is a plus 14. Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form. 15. Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level -as applicable. (ref:hirist.tech)

Location: hyderabad, IN

Posted Date: 5/15/2025