ASIC Digital Design, Sr Engineer

Job Description and Requirements We are seeking a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs. The candidate will be part of a highly experienced mixed-signal design and verification team, involved in verifying current and next-generation PAM-based SerDes products. The position offers an excellent opportunity to work with a skilled team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs, from specification development to functional and performance testing on prototype test-chips. Main Responsibilities: Writing modular constrained-random Verilog and SystemVerilog testbenches Performing functional coverage Assertion coverage and code coverage Creating and tracking test plans Evaluating failure cases and running gate-level simulations Key Qualifications: MSEE or BSEE with 2 years of digital verification experience in the industry Hands-on experience in writing test cases in Verilog and SystemVerilog Familiarity with code quality metrics Preferred Experience / Knowledge: High-speed digital & mixed-signal design & verification Asynchronous clock domain crossing Familiarity with UVM methodology and verification using VCS/Verdi Good organization and communication skills At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars, Artificial Intelligence, the cloud, 5G, and the Internet of Things are ushering in the Era of Smart Everything. We power it all with the world’s most advanced technologies for chip design and software security. Our Silicon IP business integrates capabilities into SoCs faster, offering the broadest portfolio of silicon IP—pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors—helping customers meet performance, power, and size requirements quickly and with reduced risk. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment regardless of race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Job Details Category: Engineering Country: Italy Subcategory: ASIC Digital Design Hire Type: Employee Requisition Number: 50550BR Location: Pavia, Italy J-18808-Ljbffr

Location: provincia-di-pavia, IT

Posted Date: 5/2/2025