Design Verification Engineer - UVM

Job Title : Design Verification (DV) Engineer Experience : 8-12 Years Location : [Specify Location] Employment Type : Full-time Job Summary : We are seeking a highly skilled Design Verification Engineer with 8-12 years of experience to contribute as an individual contributor in our cutting-edge verification projects. The ideal candidate will have strong SystemVerilog (SV) and Universal Verification Methodology (UVM) expertise, excellent coding skills in any programming language, and a solid understanding of fundamental digital design concepts. Knowledge of any industry-standard protocols (e.g., PCIe, USB, Ethernet, DDR, AMBA, etc.) is a plus. Key Responsibilities : - Develop verification plans, testbenches, and environments using SystemVerilog UVM. - Write and execute directed and constrained-random tests to verify complex digital designs. - Develop assertions and coverage models to ensure verification completeness. - Debug failures, analyze simulation results, and collaborate with design teams to resolve issues. - Work with functional coverage, code coverage, and assertion coverage to track verification progress. - Develop and maintain automated test environments and regression setups. - Optimize simulation performance and ensure testbench efficiency. - Collaborate with architects, RTL designers, and other verification engineers to ensure robust design validation. - Contribute to best practices in verification methodology, scripting, and automation. Required Skills & Qualifications : - 8-12 years of experience in ASIC/FPGA design verification. - Strong expertise in SystemVerilog (SV) and UVM methodology. - Strong understanding of digital design fundamentals, RTL design, and SoC architectures. - Excellent coding skills in Python, C/C++, Perl, Tcl, or Shell scripting for automation and testbench enhancements. - Experience in functional coverage, assertion-based verification (SVA), and formal verification techniques. - Knowledge of any industry-standard protocol (e.g., PCIe, USB, Ethernet, DDR, AMBA, MIPI, etc.) is a plus. - Proficiency in EDA tools such as Synopsys VCS, Cadence Incisive/Xcelium, or Mentor QuestaSim. - Experience with version control (Git, Perforce) and CI/CD integration for verification workflows is a plus. - Strong debugging, analytical, and problem-solving skills. - Ability to work independently as an individual contributor while collaborating with cross-functional teams. Nice-to-Have Skills : - Exposure to Formal Verification (JasperGold, VC Formal, or similar tools). - Experience with hardware emulation or FPGA-based prototyping. - Knowledge of high-speed interfaces and memory controllers. - Understanding of RISC-V, ARM, or GPU architectures. (ref:hirist.tech)

Location: in, IN

Posted Date: 5/1/2025